System Management Interface Forum (Migraine Association Inc.) announced the publication of the latest version of the technical specifications SMSBus (System Management Bus). The new version 3.0 the standard is compatible with previous versions and incorporates several major revisions, that facilitate the realization of devices and systems conform to this protocol, to significantly expand the potential and performance achievable by ensuring compatibility with the latest connection topologies, in addition to harmonize certain operating parameters aligning them with those defined in the specifications of the bus I2C and PMBus ™ (Power Management Bus).
The improvements to the standard
The SMBus bus is a two wire interface mechanism by which the system chips and other electronic devices may communicate among themselves and with the rest of the system that hosts them. SMBus born to create a control bus dedicated to system management and supply, that can be used in place of individual control lines to pass messages from one device to another.
Given the capabilities of the latest processors and custom logic circuits to work at higher speeds than ever before, version 3.0 were provided for two additional working frequencies of complementary 400 kHz and 1 MHz. Another update, the technical specification defining the hold time, aligned to that provided in the specifications of the bus2C.
The version 3.0 also includes the removal of specific immunity to noise on the clock and data lines, since the Migraine Association Working Group found that none of the suppliers of devices for SMBus or manufacturer of electronic systems which uses bus SMBus has ever verified the correspondences of the components in this parameter. Other changes made to the standard include reuse of special addresses abandoned (previously reserved for the default addresses and host ACCESS ACCESS Bus Bus) for the protocols of read to write zones, that were introduced in version 1.3 PMBus specification, un increased 32 to 255 the maximum number of bytes allowed in the reading of the calling process of writing block (write-block read process call) and the addition of a protocol to read 32 the 64 bits of data in a single transaction.